Fintronic Super FinSim v9.3.30 英文正式版(線性FinSim Verilog仿真器軟體)

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商品編號: CAM0344
商品名稱: Fintronic Super FinSim v9.3.30
商品分類: 工程繪圖、計算、分析軟體
語系版本: 英文正式版
商品類型: 線性FinSim Verilog仿真器軟體
運行平台: WIN 9x/WIN ME/WIN NT/WIN 2000/WIN XP/WIN 2003
更新日期: 2008-05-24
光碟片數: 1片CD光碟
銷售價格: $100元

Fintronic Super FinSim v9.3.30 英文正式版(線性FinSim Verilog仿真器軟體)


破解說明:

破解檔放置於crack夾內,請將破解檔複製於主程式的安裝目錄內既可破解
內容說明:

Super-FinSim是頂級的線性FinSim Verilog仿真器,從1993年放出第一款FinSim Verilog
仿真器至今,FinSim Verilog已經引入了許多嶄新的功能:混合編譯和解釋型仿真,仿真
工廠可以讓工程師管理數以百計的同步仿真、分離和增量編譯、高性能保存和重啟、直接
集成C代碼,無須PLI。
英文說明:

Fintronic USA Inc. is a provider of high performance
Electronic Design Automation (EDA) tools. These tools are
crucial for the design of digital circuits. The first step
in the design of a digital circuit is to formally describe
the desired functionality of the circuit in a Hardware
Design Language, such as Verilog HDL. This description of
the circuit is used as input to a simulator which will
enable the designer to find out whether the described
circuit is indeed what is needed. If not, the specification
(in the form of the Verilog description) is modified until
it becomes acceptable. Once satisfied with the
functionality, the designer refines and details this
description to lower levels of abstraction (the "register
transfer level" and the "gate level"), with the ultimate
goal of creating a very simple description of the circuit
which can then be sent to the fabrication facilities where
the actual silicon chips are produced. During this process
of refining the description of the design, the design
engineer has to continue to simulate the circuit to ensure
that the original functionality is still maintained.

Given the increased complexity of modern day chips and the
critical importance of market timing, the electronics
industry is craving for increased verification throughput
which can reduce the turnaround time of the design cycles.
Fintronic USA addresses these issues by providing Super
FinSim, which is one of the most accurate and fast Verilog
simulators in the industry. The simulation speed is achieved
by using a mixed compiled and interpreted event driven
simulator in conjunction with the Enhanced Cycle Simulation
Technology. The main gain in throughput is achieved by using
FinFarm, the simulation farm management tool. Super FinSim
is especially fit for being used in a simulation farm
because it uses little memory and the results it produces
are compact when compared with the competitionn.

Along with its Verilog simulators Fintronic USA provides
other related EDA tools which help the design engineer
during the design cycle such as support for FinMath, a
superset of Verilog that supports mathematical descriptions,
and FinCov, a code coverage tool that provides the user with
feedback regarding the quality of the test vectors used to
verify the digital circuit, by reporting how many times each
line is executed. Another extremely useful tool is FinVA
which allows users to syntactically and semantically verify
a Verilog description and create an attributed intermediate
format which can be used in conjunction with the FinVFI
package to create any tool for Verilog
analysis/synthesis/verification.

Super-FinSim is Fintronic's top performance, fully compliant
Verilog simulator. It supports PLI 1.0, SDF, VCD, SystemC,
FinMath and provides through integration with third party
source level debuggers, waveform displays etc. a complete
simulation environment on all popular platforms. FinSim
provides the flexibility of mixed compiled and interpreted
simulation and an efficient incremental compilation.

Fintronic has a mission to supply the highest performance
Verilog HDL simulators available for full language design
verification and timing simulation. It is privately held and
privately funded.



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